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Freescale Semiconductor /MKW21Z4 /XCVR_TSM_REGS /OVRD0

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Interpret as OVRD0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)BB_LDO_HF_EN_OVRD_EN 0 (BB_LDO_HF_EN_OVRD)BB_LDO_HF_EN_OVRD 0 (0)BB_LDO_ADCDAC_EN_OVRD_EN 0 (BB_LDO_ADCDAC_EN_OVRD)BB_LDO_ADCDAC_EN_OVRD 0 (0)BB_LDO_BBA_EN_OVRD_EN 0 (BB_LDO_BBA_EN_OVRD)BB_LDO_BBA_EN_OVRD 0 (0)BB_LDO_PD_EN_OVRD_EN 0 (BB_LDO_PD_EN_OVRD)BB_LDO_PD_EN_OVRD 0 (0)BB_LDO_FDBK_EN_OVRD_EN 0 (BB_LDO_FDBK_EN_OVRD)BB_LDO_FDBK_EN_OVRD 0 (0)BB_LDO_VCOLO_EN_OVRD_EN 0 (BB_LDO_VCOLO_EN_OVRD)BB_LDO_VCOLO_EN_OVRD 0 (0)BB_LDO_VTREF_EN_OVRD_EN 0 (BB_LDO_VTREF_EN_OVRD)BB_LDO_VTREF_EN_OVRD 0 (0)BB_LDO_FDBK_BLEED_EN_OVRD_EN 0 (BB_LDO_FDBK_BLEED_EN_OVRD)BB_LDO_FDBK_BLEED_EN_OVRD 0 (0)BB_LDO_VCOLO_BLEED_EN_OVRD_EN 0 (BB_LDO_VCOLO_BLEED_EN_OVRD)BB_LDO_VCOLO_BLEED_EN_OVRD 0 (0)BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_EN 0 (BB_LDO_VCOLO_FASTCHARGE_EN_OVRD)BB_LDO_VCOLO_FASTCHARGE_EN_OVRD 0 (0)BB_XTAL_PLL_REF_CLK_EN_OVRD_EN 0 (BB_XTAL_PLL_REF_CLK_EN_OVRD)BB_XTAL_PLL_REF_CLK_EN_OVRD 0 (0)BB_XTAL_DAC_REF_CLK_EN_OVRD_EN 0 (BB_XTAL_DAC_REF_CLK_EN_OVRD)BB_XTAL_DAC_REF_CLK_EN_OVRD 0 (0)BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_EN 0 (BB_XTAL_AUXPLL_REF_CLK_EN_OVRD)BB_XTAL_AUXPLL_REF_CLK_EN_OVRD 0 (0)SY_VCO_AUTOTUNE_EN_OVRD_EN 0 (SY_VCO_AUTOTUNE_EN_OVRD)SY_VCO_AUTOTUNE_EN_OVRD 0 (0)SY_PD_CYCLE_SLIP_LD_EN_OVRD_EN 0 (SY_PD_CYCLE_SLIP_LD_EN_OVRD)SY_PD_CYCLE_SLIP_LD_EN_OVRD 0 (0)SY_VCO_EN_OVRD_EN 0 (SY_VCO_EN_OVRD)SY_VCO_EN_OVRD

BB_LDO_VTREF_EN_OVRD_EN=0, SY_VCO_AUTOTUNE_EN_OVRD_EN=0, BB_XTAL_PLL_REF_CLK_EN_OVRD_EN=0, BB_LDO_PD_EN_OVRD_EN=0, BB_LDO_BBA_EN_OVRD_EN=0, BB_LDO_FDBK_EN_OVRD_EN=0, SY_VCO_EN_OVRD_EN=0, BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_EN=0, BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_EN=0, BB_XTAL_DAC_REF_CLK_EN_OVRD_EN=0, BB_LDO_FDBK_BLEED_EN_OVRD_EN=0, BB_LDO_VCOLO_BLEED_EN_OVRD_EN=0, BB_LDO_HF_EN_OVRD_EN=0, SY_PD_CYCLE_SLIP_LD_EN_OVRD_EN=0, BB_LDO_ADCDAC_EN_OVRD_EN=0, BB_LDO_VCOLO_EN_OVRD_EN=0

Description

TSM OVERRIDE REGISTER 0

Fields

BB_LDO_HF_EN_OVRD_EN

Override control for BB_LDO_HF_EN

0 (0): Normal operation.

1 (1): Use the state of BB_LDO_HF_EN_OVRD to override the signal “bb_ldo_hf_en”.
BB_LDO_HF_EN_OVRD

Override value for BB_LDO_HF_EN
BB_LDO_ADCDAC_EN_OVRD_EN

Override control for BB_LDO_ADCDAC_EN

0 (0): Normal operation.

1 (1): Use the state of BB_LDO_ADCDAC_EN_OVRD to override the signal “bb_ldo_adcdac_en”.
BB_LDO_ADCDAC_EN_OVRD

Override value for BB_LDO_ADCDAC_EN
BB_LDO_BBA_EN_OVRD_EN

Override control for BB_LDO_BBA_EN

0 (0): Normal operation.

1 (1): Use the state of BB_LDO_BBA_EN_OVRD to override the signal “bb_ldo_bba_en”.
BB_LDO_BBA_EN_OVRD

Override value for BB_LDO_BBA_EN
BB_LDO_PD_EN_OVRD_EN

Override control for BB_LDO_PD_EN

0 (0): Normal operation.

1 (1): Use the state of BB_LDO_PD_EN_OVRD to override the signal “bb_ldo_pd_en”.
BB_LDO_PD_EN_OVRD

Override value for BB_LDO_PD_EN
BB_LDO_FDBK_EN_OVRD_EN

Override control for BB_LDO_FDBK_EN

0 (0): Normal operation.

1 (1): Use the state of BB_LDO_FDBK_EN_OVRD to override the signal “bb_ldo_fdbk_en”.
BB_LDO_FDBK_EN_OVRD

Override value for BB_LDO_FDBK_EN
BB_LDO_VCOLO_EN_OVRD_EN

Override control for BB_LDO_VCOLO_EN

0 (0): Normal operation.

1 (1): Use the state of BB_LDO_VCOLO_EN_OVRD to override the signal “bb_ldo_vcolo_en”.
BB_LDO_VCOLO_EN_OVRD

Override value for BB_LDO_VCOLO_EN
BB_LDO_VTREF_EN_OVRD_EN

Override control for BB_LDO_VTREF_EN

0 (0): Normal operation.

1 (1): Use the state of BB_LDO_VTREF_EN_OVRD to override the signal “bb_ldo_vtref_en”.
BB_LDO_VTREF_EN_OVRD

Override value for BB_LDO_VTREF_EN
BB_LDO_FDBK_BLEED_EN_OVRD_EN

Override control for BB_LDO_FDBK_BLEED_EN

0 (0): Normal operation.

1 (1): Use the state of BB_LDO_FDBK_BLEED_EN_OVRD to override the signal “bb_ldo_fdbk_bleed_en”.
BB_LDO_FDBK_BLEED_EN_OVRD

Override value for BB_LDO_FDBK_BLEED_EN
BB_LDO_VCOLO_BLEED_EN_OVRD_EN

Override control for BB_LDO_VCOLO_BLEED_EN

0 (0): Normal operation.

1 (1): Use the state of BB_LDO_VCOLO_BLEED_EN_OVRD to override the signal “bb_ldo_vcolo_bleed_en”.
BB_LDO_VCOLO_BLEED_EN_OVRD

Override value for BB_LDO_VCOLO_BLEED_EN
BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_EN

Override control for BB_LDO_VCOLO_FASTCHARGE_EN

0 (0): Normal operation.

1 (1): Use the state of BB_LDO_VCOLO_FASTCHARGE_EN_OVRD to override the signal “bb_ldo_vcolo_fastcharge_en”.
BB_LDO_VCOLO_FASTCHARGE_EN_OVRD

Override value for BB_LDO_VCOLO_FASTCHARGE_EN
BB_XTAL_PLL_REF_CLK_EN_OVRD_EN

Override control for BB_XTAL_PLL_REF_CLK_EN

0 (0): Normal operation.

1 (1): Use the state of BB_XTAL_PLL_REF_CLK_EN_OVRD to override the signal “bb_xtal_pll_ref_clk_en”.
BB_XTAL_PLL_REF_CLK_EN_OVRD

Override value for BB_XTAL_PLL_REF_CLK_EN
BB_XTAL_DAC_REF_CLK_EN_OVRD_EN

Override control for BB_XTAL_DAC_REF_CLK_EN

0 (0): Normal operation.

1 (1): Use the state of BB_XTAL_DAC_REF_CLK_EN_OVRD to override the signal “bb_xtal_dac_ref_clk_en”.
BB_XTAL_DAC_REF_CLK_EN_OVRD

Override value for BB_XTAL_DAC_REF_CLK_EN
BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_EN

Override control for BB_XTAL_AUXPLL_REF_CLK_EN

0 (0): Normal operation.

1 (1): Use the state of BB_XTAL_AUXPLL_REF_CLK_EN_OVRD to override the signal “bb_xtal_auxpll_ref_clk_en”.
BB_XTAL_AUXPLL_REF_CLK_EN_OVRD

Override value for BB_XTAL_AUXPLL_REF_CLK_EN
SY_VCO_AUTOTUNE_EN_OVRD_EN

Override control for SY_VCO_AUTOTUNE_EN

0 (0): Normal operation.

1 (1): Use the state of SY_VCO_AUTOTUNE_EN_OVRD to override the signal “sy_vco_autotune_en”.
SY_VCO_AUTOTUNE_EN_OVRD

Override value for SY_VCO_AUTOTUNE_EN
SY_PD_CYCLE_SLIP_LD_EN_OVRD_EN

Override control for SY_PD_CYCLE_SLIP_LD_EN

0 (0): Normal operation.

1 (1): Use the state of SY_PD_CYCLE_SLIP_LD_EN_OVRD to override the signal “sy_pd_cycle_slip_ld_en”.
SY_PD_CYCLE_SLIP_LD_EN_OVRD

Override value for SY_PD_CYCLE_SLIP_LD_EN
SY_VCO_EN_OVRD_EN

Override control for SY_VCO_EN

0 (0): Normal operation.

1 (1): Use the state of SY_VCO_EN_OVRD to override the signal “sy_vco_en”.
SY_VCO_EN_OVRD

Override value for SY_VCO_EN

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data